View QX1101_7805686.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

secret distinction: to: from: page: 52 version : 1.6 dvb - s receiver ic gx1101 family products specification hangzhou guoxin science and technology co.,ltd 2005. 2 v1.6 free datasheet http://www..net/
gx1101 family 2 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com caution this document is preliminary and is subject to change. contact a guoxin science , re presentative to determine if this is the current information on this device. the information contained in this document has been carefully checked and is believed to be reliable. however , guoxin science makes no guarantee or warranty concerning the accura cy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, it guoxin science does not guarantee that the use of any information contained herein will not infringe upon the pate nt , trademark, copyright, mask work right or other rights of third parties, and no patent or other license is implied hereby. this document does not in any way extend guoxin science warranty on any product beyond that set forth in its standard terms and c onditions of sale. guoxin science reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. life support applications: guoxin science products are not intended for use ad c ritical components in life support appliances , devices, or systems in which the failure of a guoxin science product to perform could be expected to result in personal injury. guoxin science reserves the right to do any kind of modifications in this datas heet regarding hardware or software implementations without notice. free datasheet http://www..net/
gx1101 family 3 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com qpsk link ic with a/d converter gx1101p description the gx1101p is a complete single - chip channel receiver for satellite television reception, which conforms to dv b - s standard (ets 300 421) . it consists of two a/d converters for i - input and q - input, qpsk demodulator, and a forward error correction (fec). it supports high speed scanning mode for blind symbol rate and code rate acquisition, which allows all signals fr om a given satellite to be capture d for channel frequency, symbol rate and code rate without any known information. minimal software is required to control the chip because of the built - in automatic search functions. the carrier recovery loop and timing re covery loop are fully digital, which means that no external feedback loop is required. on - chip acquisition range is up to 45mhz. the fec unit is compliant with the dvb - s specification. processing is fully digital. the high sampling rate (up to 90m) facili tates the implementation of low - cost, direct conversion tuners. the gx1101p also provides outputs, such as noise - free serial bus dedicated to tuner control, which will ease the design of good quality application boards. to sum up, the gx1101p is an excelle nt choice for satellite receivers, set - top boxes and satellite tuners. free datasheet http://www..net/
gx1101 family 4 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com key features ? qpsk demodulator and fec conform to ebu specification for dvb - s. ? high performance integrated 6 - bit 90mhz dual - adc. ? high speed scanning mode for blind symbol rate/c ode rate acquisition. ? integrated pll clock generation using external low cost passive crystal. ? agc output with pdm mode. ? digital cancellation of a/d offset. ? interpolating and anti - alias filters support 1 to 45mbaud symbol rates. ? full digital timing recover y loop with lock detector. ? full digital carrier recovery loop with lock detector. acquisition range up to 45mhz. ? digital nyquist root filter with roll - off of 0.35. ? viterbi soft decoder with constraint length k=7, rate=1/2. automatic code rate search or p rogrammable within 1/2, 2/3, 3/4, 5/6 and 7/8. ? automatic spectrum inversion ambiguity resolution. ? automatic frame synchronization . ? convolutional deinterleaver, reed solomon decoder and de - scrambler according to dvb - s specifications. ? channel quality estimat ion. ? programmable parallel and serial output interface. ? diseqc tm v2.2 modulation output for full control of lnb and dish. ? advanced software interface for convenient software control. ? serial 2 - wire bus interface and repeater. ? bist. ? 64 - pin lqfp package. ? appl ications ? satellite digital television receivers and set - top boxes. ? satellite digital television tuner. free datasheet http://www..net/
gx1101 family 5 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com contents caution ................................ ................................ ................................ ................................ ............ 2 1 function overvie w ................................ ................................ ................................ ............. 8 1.1 adc ................................ ................................ ................................ ................................ ....... 8 1.2 qpsk d emodulator ................................ ................................ ................................ ............ 8 1.2.1 automatic gain control ................................ ................................ ................................ 8 1.2.2 carrier recovery ................................ ................................ ................................ ........... 8 1.2.3 anti - alias filter and matched filter ................................ ................................ ............ 8 1. 2.4 timing recovery ................................ ................................ ................................ ........... 8 1.2.5 signal quality indicator ................................ ................................ ................................ 9 1.3 f orward e rror c orrection ................................ ................................ ............................... 9 1.3.1 viterbi decoder ................................ ................................ ................................ ............. 9 1.3.2 synchronization ................................ ................................ ................................ ............ 9 1.3.3 convolutional deinterleaver ................................ ................................ ........................ 9 1.3.4 reed - solomon decoder ................................ ................................ .............................. 9 1.3.5 sync byte matching and descrambling ................................ ................................ .. 10 1.4 b lind s earch m ode ................................ ................................ ................................ ........... 10 1.5 t ransport s tream o utput i nterface ................................ ................................ ............ 10 1.6 c ontrol ................................ ................................ ................................ .............................. 10 1.6.1 advanced so ftware interface ................................ ................................ .................... 10 1.6.2 serial 2 - wire control bus ................................ ................................ .......................... 11 1.6.3 2 - wire bus repeater ................................ ................................ ................................ .. 11 1.6.4 diseqc tm control ................................ ................................ ................................ ....... 12 2 gx1101p initializati on ................................ ................................ ................................ ...... 14 2.1 c lock g eneration ................................ ................................ ................................ ............. 14 2.2 adc c onfiguration ................................ ................................ ................................ .......... 14 2.3 s tandby m ode ................................ ................................ ................................ .................... 15 2.4 c hip id ................................ ................................ ................................ ................................ . 15 3 tuner control ................................ ................................ ................................ .................... 16 3.1 s imple c hannel c hange s equence ................................ ................................ ................. 16 3.2 c hannel c hange s equence with a new s ymbol r ate ................................ ................... 16 3.3 b lind s earch m ode ................................ ................................ ................................ ........... 17 3.4 t uner c ontrol r egisters ................................ ................................ ................................ 18 3.4.1 repeater and rese t control register 30h ................................ ................................ . 18 3.4.2 gpop0 control register 31h ................................ ................................ ....................... 18 3.4.3 gpop1 control register 32h ................................ ................................ ....................... 19 3.4.4 state indicator register 34h ................................ ................................ ......................... 19 3.4.5 state indicator with search mode register 35h ................................ ........................ 19 4 diseqc tm control ................................ ................................ ................................ .............. 21 free datasheet http://www..net/
gx1101 family 6 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 4.1 d i se q c tm c ontrol r ead /w rite r egisters ................................ ................................ .... 21 4.1.1 diseqc tm mode control register10h ................................ ................................ ........ 21 4.1.2 diseqc tm ratio register 11h ................................ ................................ ...................... 21 4.1.3 diseqc tm instruction register 12h ................................ ................................ ............. 22 4.1.4 diseqc tm control register 1bh ................................ ................................ .................. 22 4.2 d i se q c tm c ontrol r ead r egisters ................................ ................................ ................ 23 4.2.1 diseqc tm interrupt indicators register 1ch ................................ ............................. 23 4.2.2 diseqc tm response register 1eh ................................ ................................ ............. 23 5 qpsk demodulator ................................ ................................ ................................ ........... 24 5.1 agc r egisters ................................ ................................ ................................ ................... 24 5.1.1 agc control register 40h ................................ ................................ ............................ 24 5.1.2 agc standard power register 41h ................................ ................................ ............ 25 5.1.3 s ignal intensity indicator register 42h ................................ ................................ ....... 25 5.2 c arrier r ecovery r egisters ................................ ................................ ........................... 25 5.2.1 carrier frequency error1 register 50h & 51 h ................................ ......................... 25 5.2.2 carrier frequency error2 register 52h & 53h ................................ .......................... 26 5.2.3 signal quality indicator register 54h ................................ ................................ ......... 26 5.2.4 qpsk function switch register 55h ................................ ................................ .......... 27 5.2.5 qpsk spectral inversion register 58h ................................ ................................ ...... 27 5.2.6 carrier r ecovery loop parameter register 59h ................................ ...................... 27 5.3 t iming r ecovery r egisters ................................ ................................ .............................. 28 5.3.1 blind search mode control register 60h ................................ ................................ ... 28 5.3.2 symbol rate register 61h 62h ................................ ................................ ................... 28 5.3.3 timing recovery loop parameter register 69h ................................ ....................... 28 5.3.4 blind search step size register 6bh ................................ ................................ ......... 29 6 fec ................................ ................................ ................................ ................................ ............. 30 6.1 v iterbi d ecoder r egisters ................................ ................................ .............................. 30 6.1.1 viterbi code rate register 84h ................................ ................................ ................... 30 6.1.2 viterbi mode register 85h ................................ ................................ ............................ 30 6.1.3 viterbi error mode regist er 80h ................................ ................................ .................. 31 6.1.4 viterbi error count register 81h & 82h & 83h ................................ ......................... 31 6.2 rs d ecoder r egisters ................................ ................................ ................................ ...... 32 6.2.1 rs decode error mode register a0h ................................ ................................ ......... 32 6.2.2 rs decode error count register a1h & a2h ................................ ........................... 32 7 mpeg packet dat a output ................................ ................................ .............................. 34 7.1 d ata o utput c ontrol r egisters ................................ ................................ ..................... 34 7.1.1 data control register b0h ................................ ................................ ............................ 34 7.1.2 data format control register b1h ................................ ................................ .............. 34 7.2 o utput i n p arallel m ode ................................ ................................ ................................ . 35 7.3 o utput i n s erial m ode ................................ ................................ ................................ ..... 36 free datasheet http://www..net/
gx1101 family 7 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 8 application notes ................................ ................................ ................................ ............. 38 8.1 r ecommended o perating c onditions ................................ ................................ ............. 38 8.2 a bsolute m aximum r a tings ................................ ................................ ............................ 38 8.3 dc e lectronic c haracteristics ................................ ................................ ..................... 38 8.4 gx1101p r egister m ap ................................ ................................ ................................ ..... 39 8.4.1 read/write register map ................................ ................................ .............................. 39 8.4.2 read only register map ................................ ................................ ............................... 40 8.5 a pplication s chematic ................................ ................................ ................................ ...... 41 8.5.1 adc external circuit ................................ ................................ ................................ ...... 41 8.5.2 crystal and pll ................................ ................................ ................................ .............. 42 8.5.3 agc circuit ................................ ................................ ................................ ...................... 42 8.5.4 lnb controller ................................ ................................ ................................ ................. 43 8.5.5 power sequence ................................ ................................ ................................ ............ 44 9 block diagram ................................ ................................ ................................ ................... 45 10 application diagram ................................ ................................ ................................ ... 46 11 pin information ................................ ................................ ................................ .............. 47 11.1 p in d iagram ................................ ................................ ................................ ........................ 47 11.2 p in d escription ................................ ................................ ................................ .................. 48 12 package information ................................ ................................ ................................ .. 51 free datasheet http://www..net/
gx1101 family 8 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 1 function overview 1.1 adc the gx1101p contains dual 6 - bit 100mhz a/d converters, which have optional single - ended/differential input and programmed full - scale input range of 0.25v, 0.5v and 0.75v. the fixed sampling clock 90mhz is provided on - chip using a programmable pll needing only a low cost crystal. 1.2 qpsk demodulator the qpsk demodulator in the gx1101p consists of automatic gain control (agc), carrier recovery, anti - alias filters, matched filter, timing recovery, etc. 1.2.1 automatic gain control the power of the input signal is compared to the programmable standard threshold, and the differenc e is integrated. the integrated difference is then converted into a modulation signal to drive the agc output. it needs only a simple rc filter outside the chip. the dynamic characters and jitter performance of the agc will be the best. 1.2.2 carrier recovery t he tracking range of the carrier recovery can exceed one time symbol rate, up to 45mhz. t herefore the search of the initial channel frequency can go alone without reconfiguring the tuner even when there are relatively large carrier offsets introduced by t he low noise block (lnb). 1.2.3 anti - alias filter and matched filter anti - alias filter is designed for all symbol rates from 1 to 45mbaud. the gx1101p selects the most efficient anti - alias filters automatically according to the given symbol rate. the matched fi lter is a root - raised - cosine filter with roll - off factor 0.35. 1.2.4 timing recovery free datasheet http://www..net/
gx1101 family 9 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com in the normal mode, the only thing needs to do is to configure the symbol rate, and the on - chip advanced software interface (adsi) will automatically change it to the data style used in timing recovery. c onsequently , the recovery loop will work out quickly. 1.2.5 signal quality indicator the signal quality indicator shows the quality estimation of the signals into gx1101p. it can be used during the installation of the front - end, inclu ding the antenna, lnb, cable and tuner. 1.3 forward error correction 1.3.1 viterbi decoder the convolutional code is generated by the polynomial 133 , 171 ? ? y x g g , with rates 1/2, 2/3, 3/4, 5/6 and 7/8. the viterbi decoder block can search the code rate autom atically. 1.3.2 synchronization in dvb standard 204 bytes constitute a packet, and the first byte of each packet is a sync word ( i.e. 0xb8 or 0x47 ). the sync word of 0xb8 occurs once every 8 packets, and the other 7 sync words are 0x47. the synchronize r can establish synchronization in a short time w ith an effective algorithm . 1.3.3 convolutional deinterleaver to mitigate any burst or impulse noise and increase the error correction ability of the reed - solomon fec code, the bytes are interleaved after rs encoding at the transmitter, so it must be deinterleav ed before rs decoding at the receiver. the convolutional deinterleaver is 17 12 (b=12,m=17), and there are 204 bytes in every packet. 1.3.4 reed - solomon decoder the input blocks are 204 - byte long with 16 parity bytes in dvb, and up to 8 byte errors may be correc ted. rs decoder also supplies s tatistic performance, e.g. bit error rate after viterbi decoder. free datasheet http://www..net/
gx1101 family 10 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 1.3.5 sync byte matching and descrambling i n dvb, the frame header is synchronized at the start of every 8 packets before de - scrambling . before rs encoding in transm itter data will be scrambled, so it must be de - scrambled after rs decoding in receiver . 1.4 blind search mode the gx1101p can work in blind search mode when the channel frequency, symbol rate and code rate are unknown. for a given channel frequency range, the chip will search the signals quickly with the simple control of the software. the search time is less than five minutes. 1.5 transport stream output interface the gx1101p offers several kinds of mpeg/ts output formats ( dvb - specified common interface format ), and a specific parallel /serial format. there are d7, d6, d5, d4, d3, d2, d1, d0, datvld, error, sync, bytclk output pins. d7~d0: parallel data output, d7 in serial mode. bytclk: byte clock in parallel mode while bit clock in serial mode whose polarity can be configured. datvld: high if valid. strobe signal that indicates whether the byte (bit in serial mode) supplied on d7~d0 (d7 in serial mode), to be clocked in by the active edge of bytclk, is one of the 188 valid bytes of the mpeg packet. error: high if valid. this signal goes high during transmission of an mpeg/ts packet if this packet contains errors that could not be corrected by rs decoder. sync: high if valid. this signal flags the first byte (bit in serial mode) of an mpeg/ts packet. 1.6 control 1.6.1 advanc ed software interface free datasheet http://www..net/
gx1101 family 11 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com the gx1101p has an advanced software interface (adsi) to simplify the software design. the adsi maps high level inputs such as symbol rate in mbaud to low level on - chip register settings, and as well as maps low level register setting s to high level symbol rate outputs for software. 1.6.2 serial 2 - wire control bus the gx1101p is controlled via a serial 2 - wire bus and is a pure slave. its 7 - bit chip address is 110100a , where a is determined by applying vdd or vss to the devaddr pin. so its 8 - bit write address is 110100a0 and its 8 - bit read address is 110100a1 . the serial 2 - wire bus supports the speed up to 400khz. write and read operations are described in figure 1 and 2. scl sda start slave address r/w register address a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack by gx1101p ack by gx1101p data byte 1 ack by gx1101p scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by gx1101p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data byte 2 ack by gx1101p data byte 3 ack by gx1101p data byte n stop a figure 1 the 2 - wire bus write opera tion scl sda start slave address r/w register address a a7 a6 a5 a4 a3 a2 a1 a0 ack by gx1101p ack by gx1101p scl d7 d6 d5 d4 d3 d2 d1 d0 ack by micro data byte n stop stop sda start slave address r/w ack by gx1101p d7 d6 d5 d4 d3 d2 d1 d0 data byte 1 a ack by micro figure 2 the 2 - wire bus read operation 1.6.3 2 - wire bus repeater free datasheet http://www..net/
gx1101 family 12 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com the goal of this block is to remove all disturbance s to the tuner and thus improve s tuner performance. the tuner can connect to pins sclt and sdat, as illustrated i n figure 3. when enabled, the repeater behaves as a fully bidirectional link between the main 2 - wire bus (scl, sda) and the private bus (sclt, sdat). when disabled, pins sclt and sdat are completely isolated from the main 2 - wire bus and are inactive (high level). master scl sda 1 5 1 4 gx1101p internal registers sdat sclt 6 7 tuner repeater on/off figure 3 2 - wire bus repeater 1.6.4 diseqc tm control the gx1101p has the capability to send and receive diseqc tm messages, which can simplify the communication between microcontrollers and lnbs. eight registers are provided to store a message for transmission and a further eight registers are provided to store a received message. and a programmable output pin hvselect can control the horizontal/vertical polarization . the sequence of events to send and receive a message is as fo llows: 1. load the required message bytes into the diseqc_ins register. 2. load the number of bytes in diseqc tm message minus 1 in the register diseqc_mode[5:3]. 3. set diseqc_mode[2:0] = 4 to command the gx1101p to encode the data and transmit the message. 4. if no r eply required, an interrupt tx_int is generated 16ms after the last message byte has been sent and diseqc_mode[2:0] reset to 0 automatically. if reply required, gx1101p will listen for diseqc tm message 5ms after a message has been transmit and tx_int isn t free datasheet http://www..net/
gx1101 family 13 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com generated. if silent_int = 1 and end_msg_int = 0, there has been no message received. if a message has been received, end_message_int will be set and diseqc_int[7:4] indicate how many bytes have been received. the microcontroller can read the received mes sage from diseqc_resp. besides, err_int indicates an error in the received message, while par_err_int refers to a parity error. the data loaded into diseqc_ins register is retained, so that if the same message is to be repeated, the data loading stage 1 above can be omitted. but the received data in diseqc_resp will be cleared when transmitting another message. free datasheet http://www..net/
gx1101 family 14 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 2 gx1101p initialization 2.1 clock generation an integrated pll generates adc sampling clock (90.0mhz) and chip internal system clock. pll output fre quency is calculated from the following equation: ]) 0 [ _ ] 1 [ _ ( 2 * ) 2 _ ( 2 _ * k pll k pll n pll m pll xin clk ? ? ? ? where xin is the pll input crystal frequency, clk is adc sampling clock and chip internal system clock 90mhz, other parameters are according to the following registers: name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default pll kn 02h pll_k [1:0] pll_n [4:0] pll_m [8] r/w c0h pll m 03h pll_m [7:0] r/w b2h note: all registers and their default values are hexadecimal values. read/write registers are fl agged as r/w, while the read only registers are flagged as r. in order to obtain good duty cycle, pll_k is suggested to be 2 b11, while ] 50 , 2 [ mhz mhz xin ? , ] 31 , 0 [ _ ? n pll , ] 511 , 0 [ _ ? m pll . as an example, for a 4mhz crystal, the system clock frequency is 90mhz with pll_k=3 and (pll_m+2)/(pll_n+2)=90. 2.2 adc configuration the full - scale input range of adc can be programmed with the following register: name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default adc gain 04h 6 b0 adc_gain r/w 01h b1 - 0: adc_gain select the full scale input range of adc 00: 0.25vpp 01: 0.50vpp 10: 0.75vpp free datasheet http://www..net/
gx1101 family 15 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 2.3 standby mode a low power consumption mode (standby mode) can be controlled via the following register: name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default st by 01h standby ts_oen 6 b0 r/w 00h b7: standby the chip is in normal or standby mode 1: standby mode 0: normal mode chip internal blocks are shut down in standby mode, and they would resume quickly when standby mode is cancelled. b6 ts_oen ts output normal or tri - state 1 tri - state 0 normal 2.4 chip id name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default id 00h id[7:0] chip identification r 01h this register provides an identification number related to the gx1101p versi on. free datasheet http://www..net/
gx1101 family 16 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 3 tuner control 3.1 simple channel change sequence if the gx1101p is running, to i. change the channel frequency, ii. keep the symbol rate, iii. change the viterbi code rate, it is only necessary to change the tuner data and possibly the diseqc tm data. no other config urations including viterbi code rate and reset are necessary. open repeater(reg.30h=09h) & send tuner data close repeater&reset the gx1101p(reg.30h=0ah) diseqc mode reg.10h=00h(vertical) or 40h(horizontal) figure 4 simple channel change sequence 3.2 channel change sequence with a new symbol rate if the gx1101p is running, to i. change the channel frequency, ii. change the symbol rate, iii. change the viterbi code rate, it is only necessary to change the tuner data and possibly the diseqc tm data and symbol rate. no other configurations including viterbi code rate and reset are necessary. free datasheet http://www..net/
gx1101 family 17 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com open repeater(reg.30h=09h) & send tuner data close repeater&reset the gx1101p(reg.30h=0ah) diseqc mode reg.10h=00h(vertical) or 40h(hotizontal) symbol rate eg 20.0mbaud reg.62h=50h, reg.61h=00h figure 5 channel ch ange sequence with a new symbol rate 3.3 blind search mode if the signal parameters are unknown, it is easy to instruct the gx1101p to search for digital signals in the range required and report parameters, including channel and symbol rate and code rate, by s oftware programs. open repeater(reg.30h=09h) & send tuner data close repeater&reset the gx1101p(reg.30h=0ah) diseqc mode reg.10h=00h(vertical) or 40h(hotizontal) search mode reg.60h=01h read reg.35h=c0h ? n read symbol rate from reg.62h & 61h fs=reg[62h]/4+reg[61h]/1024 mbaud read reg.50h & 51h & 52h & 53h calculate the frequency compensation value reg.35h!=00h or 80h or time out y figure 6 blind search mode free datasheet http://www..net/
gx1101 family 18 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 3.4 tuner control registers 3.4.1 repeater and reset control register 30h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default glb ctrl 30h reserved rpt_time_sel cool_rst hot_rst rpter_en r/w 08h b4 - 3: rpt_ time_sel select the repeater s response time, i.e. the rise times on sdat and sclt. 00: 150ns 01: 250ns 10: 350ns 11: 450ns b2: cool_rst full reset of the chip 1: reset all registers 0: release th e full reset b1: hot_rst partial reset of the chip, automatically set low again after use. 1: reset all registers except configuration registers 0: release the partial reset b0: rpter_en switch of serial 2 - wire control bus repeater for t uner 1: on 0: off 3.4.2 gpop0 control register 31h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default gpop0 31h reserved 1 b1 po0/aud_out r/w 16h b3 - 0: po0/aud_out select gpop0 outputs 0110: audio output free datasheet http://www..net/
gx1101 family 19 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 0111: high level 1000: low level the audio signal output on the gpop0 pin indicates the signal quality during dish alignment, also see qpsk demodulator for detail. 3.4.3 gpop1 control register 32h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default gpop1 32h reserved 4 b1100 po1 r/ w 18h b0: po1 select gpop1 outputs 0: high level 1: low level 3.4.4 state indicator register 34h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default state 34h state_indicator r 00h b7: agc_lock qpsk agc lock indicator, active high b 6: carrier_lock qpsk carrier lock indicator, active high b5: timing_lock qpsk timing lock indicator, active high b4: vit_lock viterbi lock indicator, active high b3: vit_fail viterbi fail indicator, active high b2: dei_lock deinterlea ver lock indicator, active high b1: rs_fail rs decoder fail indicator, active high b0: dsc_lock de - scrambler lock indicator, active high 3.4.5 state indicator with search mode register 35h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default blind sta te 35h blind_state_indicator r 00h b7: qpsk_find qpsk search signal successes, active high free datasheet http://www..net/
gx1101 family 20 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com b6: fec_find fec search signal successes, active high b5: fec_fail fec search signal fails, active high b4: carrier_fail carrier recovery search s ignal fails, active high b3: timing_fail1 timing recovery search signal fails1, active high b2: timing_fail2 timing search signal fails2, active high b1: qpsk_fail qpsk search signal fails, active high b0: agc_fail agc search signal fails , active high in the blind search mode, a signal is found only if the value 8 b11000000 is read from this register. that any bit among b5 - b0 is high means no signal is found, and it is time to change the tuner data. free datasheet http://www..net/
gx1101 family 21 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 4 diseqc tm control 4.1 diseqc tm control read/w rite registers 4.1.1 diseqc tm mode control register10h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default diseqc mode 10h reserved hvselect tx_bytes diseqc_mode r/w 00h b6: hvselect h/v polarization control, to output on hvselect pin 1: horizontal 0 : vertical b5 - 3: tx_bytes number of bytes in diseqc tm instruction minus 1 b2 - 0: diseqc_mode diseqc tm mode 000: 22khz off 001: 22khz on continuous 010: burst mode C on for 12.5ms = 0 011: burst mode C modulated 1:2 for 12.5ms = 1 100: modulated with bytes from diseqc ins 101 - 111: reserved for mode 2 and 3, an interrupt is generated 16ms after the 0 or 1 burst. for mode 4, there is a 16ms delay before the message bytes, and an interrupt is generated 16ms after the last mess age byte has been sent. the requisite number of bytes must be pre - loaded into diseqc ins (register 12h) before this bit is set. 4.1.2 diseqc tm ratio register 11h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default diseqc ratio 11h diseqc_ratio r/w 2dh free datasheet http://www..net/
gx1101 family 22 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com b7 - 0: diseqc_ratio it must be programmed to set the diseqc tm output tone frequency. f out =f xtal / (4*diseqc_ratio[7:0]) 4.1.3 diseqc tm instruction register 12h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default diseqc ins 12h diseqc_ins r/w 00h b7 - 0: diseqc_ins instruction data up to eight instruction data bytes can be loaded into registers 12h~19h through this register, because the 2 - wire bus register address would increase automatically . 4.1.4 diseqc tm control register 1bh name addr b7 b6 b5 b4 b3 b2 b1 b0 fla g default diseqc ctrl 1bh reserved min_pulse max_tone min_tone r/w 0ch b3 - 2: min_pulse minimum pulse period 00: 24*diseqc_ratio 01: 26*diseqc_ratio 10: 28*diseqc_ratio 11: 30*diseqc_ratio b1: max_tone maximum tone period 0: 5.5*diseqc_ratio (16khz) 1: 6.0*diseqc_ratio (14.67khz) b0: min_tone minimum tone period 0: 3.0*diseqc_ratio (29.3khz) 1: 2.75*diseqc_ratio (32khz) free datasheet http://www..net/
gx1101 family 23 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 4.2 diseqc tm control read registers 4.2.1 diseqc tm interrupt indicators register 1ch name ad dr b7 b6 b5 b4 b3 b2 b1 b0 flag default diseqc int 1c h rx_bytes tx_ int silent_ int end_msg _int err_ int par_err _int r 00h b7 - 5: rx_bytes number of bytes received minus 1 b4: tx_int end of sending message interrupt b3: silent_int silent peri od exceeds 176ms interrupt b2: end_msg_int end of receiving message interrupt. the end of a message is identified by a silent period of about 6ms following a byte. b1: err_int receive error interrupt. b0: par_err_int parity error interrupt . 4. 2.2 diseqc tm response register 1eh name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default diseqc resp 1eh diseqc_resp r 00h b7 - 0: diseqc_resp received data up to eight received data bytes can be read from registers 1eh~25h through this register, because the 2 - wire bus register address would increase automatically . free datasheet http://www..net/
gx1101 family 24 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 5 qpsk demodulator 5.1 agc registers 5.1.1 agc control register 40h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default agc ctrl 40h freeze clk speed plr 1 b0 r/w 52h b7: freeze agc is freezed or normal 1: freezed 0: normal b6 - 5: clk select agc working frequency, default is 2 00: system clock 01: system clock divided by 2 10: system clock divided by 4 11: system clock divided by 8 the smaller rc can be selected by increasing the working frequency of agc, however the disturbances will increase at the same time. b4 - 2: speed speed control of the agc loop, default is 4 agc loop gain = k*2^ speed , k is a constant. the agc loop s converge nce rate will incr ease in exponential rate as the speed comes from 0 to 7. at the same time, it will introduce sever e jitter after the loop is locked, which maybe results in larger ber. so, in application, we d better make a balance between the loop s converge speed and bit error rate. b1: plr select the polarity , default is 1 0: positive slope i.e. rf gain proportional to agc voltage. 1: negative slope i.e. rf gain inversely proportional to agc voltage. free datasheet http://www..net/
gx1101 family 25 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 5.1.2 agc standard power register 41h name ad dr b7 b6 b5 b4 b3 b2 b1 b0 flag default agc std 41h agc_std r/w 1c h b7 - 0: agc_std agc power reference value, unsigned after the agc loop locked, intermediate - frequency signals can be enlarged by configure the agc_std a larger value, and more suffici en t use of the adc s sample precision can be made. but the signal level can t exceed the adc s full - scale, otherwise, it will deteriorate the system performance . default value is suggested. 5.1.3 signal intensity indicator register 42h name addr b7 b6 b5 b 4 b3 b2 b1 b0 flag default intensity 42h signal_intensity r 00h b7 - 0: signal_intensity signal intensity indicator, unsigned the signal intensity indicator has a value between 0 and 255 after the agc loop locked, which is almost inversely proportional to the real rf signal level. read the register to get the rf signal level (signal intensity). 5.2 carrier recovery registers 5.2.1 carrier frequency error1 register 50h & 51 h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default freq err1 l 50h freq_err1[7:0] r/w 00h b7 - 0: freq err1[7:0] low byte of the carrier frequency coarse adjustment error name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default freq err1 h 51h freq_err1[15:8] r/w 00h b7 - 0: freq_err1[15:8] high byte of the carrier frequency coarse adjustment err or it s a signed value. by configuring the registers above without the tuner operation, we can free datasheet http://www..net/
gx1101 family 26 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com compensate the carrier frequency error; by reading the registers, the values show a coarse estimation of the carrier frequency error. the relation between the re gisters and the frequency error is: 65536 _ 1 _ 1 clk sys err freq ferr ? ? the 1 ferr is the coarse estimation of the carrier frequency error, clk sys _ is the system clock (90mhz). 5.2.2 carrier frequency error2 register 52h & 53h name ad dr b7 b6 b5 b4 b3 b2 b1 b0 flag default freq err2 l 52h freq_err2[7:0] r 00h b7 - 0: freq err2[7:0] low byte of the carrier frequency fine adjustment error name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default freq err2 h 53h freq_err2[15:8] r 00h b7 - 0: fr eq_err2[15:8] high byte of the carrier frequency fine adjustment error freq err2 expresses the fine estimation of the residual carrier frequency error. the relation between the registers and the frequency error 2 ferr is: 65536 _ 2 _ 2 rate sym err freq ferr ? ? , rate sym _ is the symbol rate. the four registers 50h~53h can be read continuously, and all carrier frequency errors can be rectified by combine the two parts. 2 1 ferr ferr ferr ? ? . 5.2.3 signal quality indicator register 54h name add r b7 b6 b5 b4 b3 b2 b1 b0 flag default snr 54h snr[7:0] r 00h b7 - 0: snr[7:0] snr indicator, unsigned this register indicates the received signal quality , which can be used to facilitate the antenna setup. free datasheet http://www..net/
gx1101 family 27 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 5.2.4 qpsk function switch register 55h na me addr b7 b6 b5 b4 b3 b2 b1 b0 flag default audio derot 55h audio_on drt_on 6 b101110 r/w 6eh b7: audio_on switch of the audio function, default is 0 1: open the audio function, signal is outputted from the pin gpop0 0: cl ose the audio function, the pin gpop0 putouts low. audio signal frequency is proportional to the signal quality snr db, which can help to adjust the antenna with a beeper outside. b6: drt_on switch of the carrier frequency coarse adjustment function, default is 1. 1: on 0: off 5.2.5 qpsk spectral inversion register 58h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default iq swap 58h iq_sp 7 b0110100 r/w 34h b7 iq_sp swap i and q inputs before qpsk demodulation, default is 0. 1 swap 0 no swap swap i and q inputs before qpsk demodulation to overcome spectral inversion caused by the receiver front - end, for example through the swapping i and q wires on the board. 5.2.6 carrier recovery loop parameter register 59h name a ddr b7 b6 b5 b4 b3 b2 b1 b0 flag default crl para 59h crl_para r/w 58h free datasheet http://www..net/
gx1101 family 28 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com b7 - 0: crl_para [7:0] carrier recovery loop parameter, default is 58h. the recommended value is: 58h when viterbi code rate is 1/2 3ch when viterbi code rate i s 2/3, 3/4,5/6 or 7/8 5.3 timing recovery registers 5.3.1 blind search mode control register 60h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default blind sel 60h 7 b0000000 bld_mod r/w 00h b0: bld_mod select the blind search mode 1: blind search mode. 0: normal mode. 5.3.2 symbol rate register 61h 62h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default sym rate l 61h sym_rate [7:0] r/w ae h b7 - 0: sym_rate [7:0] low byte of the symbol rate name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default sym rate h 62h sym_rate [15:8] r/w 11h b7 - 0: sym_rate [15:8] high byte of the symbol rate suppose that sr is symbol rate in mbaud, these two registers should be configured as follows: 1024 ] 0 : 15 [ _ ? ? sr rate sym , e.g. using the default value, sr 4.42mbaud, then sym_ra te[15:0]=4.42*1024=4526=11ae(hex) so write aeh to register sym rate l and 11h to register sym rate h. reading these two registers, then calculating by the formula above, we can get the accurate symbol rate. 5.3.3 timing recovery loop parameter register 69 h free datasheet http://www..net/
gx1101 family 29 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default trl para 69h trl_para r/w 24h b7 - 0: trl_para [7:0] timing recovery loop parameter, default is 24h. the recommended value is 1eh. 5.3.4 blind search step size register 6bh name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default scan len 6bh 4 b0110 scan_len r/w 67h b3 - 0 scan_len the limit of blind search step size, default is 7. in the blind search mode, the blind search step size in software can t be larger than three times of scan_len generally. the recommended value is 2. free datasheet http://www..net/
gx1101 family 30 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 6 fec 6.1 viterbi decoder registers 6.1.1 vite rbi code rate register 84h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default vit rat cur 84h vit_rat_cur reserved r 00h b7 - 5 vit_rat_cur the code rate found by viterbi decoder 0 1/2 1 2/3 2 3/4 3 5/6 4 7/8 6. 1.2 viterbi mode register 85h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default vit mode 85h 3 b0 aut_iq vit_rat aut_rat r/w 10h b4 aut_iq automatic spectrum inversion ambiguity resolution 0 disable automatic spectrum inversion ambiguity resol ution 1 enable automatic spectrum inversion ambiguity resolution b3 - 1 vit_rat specify code rate when manual set 0 1/2 1 2/3 2 3/4 3 5/6 4 7/8 b0 aut_rat automatic code rate search 0 e nable automatic code rate search free datasheet http://www..net/
gx1101 family 31 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 1 use the code rate specified in vit rat. user can either use automatic code rate search (aut rat = 0) or specify a code rate (aut rat = 1) in vit rat. automatic code rate search (aut rat = 0) is recommend ed it i s recommended to enable automatic spectrum inversion ambiguity resolution (aut iq = 1). 6.1.3 viterbi error mode register 80h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default vit err mode 80h reserved vit_err_cnt_mod r/w 11h b4 - 0 vit_err_cnt_mod mode of error rate counter for data at the input of viterbi decoder 0xxxx disable the counter 100xx count for bit error rate 101xx count for symbol error rate 1xx00 count for 2^12 bytes 1xx01 count for 2^14 bytes 1xx10 count for 2^16 bytes 1xx11 count for 2^18 bytes 6.1.4 viterbi error count register 81h & 82h & 83h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default vit err cnt l 81h vit_err_cnt[7:0] r 00h vit err cnt m 82h vit_err_cnt[15:8] r 00h vit err cn t h 83h vit_err_cnt[23:16] r 00h vit_err_cnt [23:0] indicates the number of errors at the input of viterbi decoder. the count mode is decided by the register 80h. only when vit_err_cnt_l is read, will the vit_err_cnt_m and vit_ err_cnt_h be updated to kee p consistency . therefore, the sequence of reading these three registers should be vit_err_cnt_l, vit_err_cnt_m and vit_err_cnt_h, or vit_err_cnt_l, vit_err_cnt_h and vit_err_cnt_m. these free datasheet http://www..net/
gx1101 family 32 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com three registers represent the quality of qpsk demodulator. cnt byte cnt err vit rat vit k err qpsk _ 8 ] 0 : 23 [ _ _ _ _ ? ? ? ? in the above equation, cnt byte _ is the count period in byte. when counting for bit error rate (i.e. vit_err_cnt_mod = 100xx ), 1 ? k , and when counting for symbol error rate (i.e. vit_err_cnt_mod = 101xx ), 2 ? k . for example, if vit_err_cnt_mod = 0x11, and vit_rat = 3/4, which can be obtained in vit_rat_cur then the bit error rate is 14 ^ 2 8 ] 0 : 23 [ _ _ 4 / 3 1 _ ? ? ? ? cnt err vit ber qpsk 6.2 rs decoder registers 6.2.1 rs decode error mode register a0h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default rs err mode a0h reserved cnt_knd err_knd r/w 07h b3 - 2: cnt_knd number of packet 0: 2^12 1: 2^10 2: 2^8 3: 2^6 b1 - 0: err _knd type of error accumulated 0: uncorrectable packet error sum 1: packet error sum 2: byte error sum 3: bit error sum default: 2^10 packets, bit error sum. 6.2.2 rs decode error count register a1h & a2h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default free datasheet http://www..net/
gx1101 family 33 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com rs err cnt l a1h rs_err_cnt [7:0] r 00h rs err cnt h a2h rs_err_cnt [15:8] r 00h rs_err_cnt [15:0] shows the number of error before rs decoder. you can configure the statistic length (reg.a0h). while system is stabile , two registers can be read and the error rate can be known. bit error rate: cnt packet cnt err rs ber vit _ 8 204 ] 0 : 15 [ _ _ _ ? ? ? cnt packet _ is the statistic number. for example: reg. a0h default, the bit error rate is: 10 ^ 2 8 204 ] 0 : 15 [ _ _ _ ? ? ? cnt err rs ber vit free datasheet http://www..net/
gx1101 family 34 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 7 mpeg packet data output 7.1 data output control registers 7.1.1 data control register b0h name addr b7 b6 b5 b4 b3 b2 b1 b0 f lag default ts data ctrl b0h tei_en pkt_len head 5 b11101 r/w bdh b7: tei_en show the u ncorrectable packet error 1: set the msb of first byte of an uncorrectable packet, and clear it when the packet is corrected (default). 0: not set b6: pkt_len output data length is 188 bytes or 204 bytes 1: 188 bytes 0: 204 bytes (default) b5: head sync 1: sync b8h is replaced by 47h (default) 0: not replaced 7.1.2 data format control register b1h name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default ts fmt ctrl b1h po_en pos_en 4 b1011 rs0 1 b0 r/w ach b7: po_en output in parallel or serial mode 1: parallel (default) 0: serial b6: pos_en define the output date aligning with out put byte clock s positive edge or negative edge. parallel: free datasheet http://www..net/
gx1101 family 35 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 1: align with positive edge 0: align with negative edge (default) serial: 1: bit clock valid in low (suggested) 0: bit clock valid in high b1: rs0 ou tput clock signal configuration during parity bytes 1: d7 is low during the parity bytes. if the packet contains more than 8 errors, error only remains high during the data transmission. in parallel mode, clock remains low during the parity bytes. in seria l mode, the output bit clock always running. 0: clock is continuous and the parity bytes are transmitted. if the packet contains more than 8 errors, error remains high during the entire packet. it is suggested that set this register to ach in parallel mode and 7ch in serial mode. 7.2 output in parallel mode every packet has 188 or 204 bytes. data and other signals are clocked by the positive or negative edge of clock, referring to figure 7 and figure 8. sync datvld 188bytes byt1 if package error,the msb of byte1 is set 1 bytclk error with error without error d7-d0 47h byt2 byt3 byt4 byt187 47h pos en=0 pos en=1 tei figure 7 p arallel output ( 188 bytes/packet and 188 bytes valid) free datasheet http://www..net/
gx1101 family 36 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com sync datvld 204bytes byt1 if package error,the msb of byte1 is set 1 bytclk with error without error d7-d0 47h byt2 byt3 byt4 byt203 47h pos en=0 tei pos en=1 pos en=0 rs0=1 rs0=0 rs0=0 rs0=1 pos en=1 rs0=0 error with error without error rs0=1 188bytes figure 8 parallel output (204 bytes/packet and 188 bytes valid) 7.3 output in serial mode the serial bit stream is available on d7, and bytclk is the bit clock. d ata and other signals are cloc ked by the positive or negative edge of clock, referring to figure 9 and figure 10. sync error datvld d7 bytclk pos en=1 pos en=0 with error without error 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 188bytes byt1 byt187 if package error,the msb of byte1 is set 1 figure 9 serial output ( 188 bytes/packet and 188 bytes valid) free datasheet http://www..net/
gx1101 family 37 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com sync error datvld bytclk pos en=1 pos en=0 with error without error 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 204bytes byt1 byt203 if package error,the msb of byte1 is set 1 rs0=0 with error without error rs0=1 d7 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 204bytes byt1 byt203 0 rs0=1 rs0=0 188bytes figure 10 serial output (204 bytes/packet and 188 by tes valid) free datasheet http://www..net/
gx1101 family 38 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 8 application notes 8.1 recommended operating conditions parameters pins min typ max units 1.8v power supply voltage 5,14,28,36,42,56,58,64 1.62 1.80 1.98 v 1.8v power supply current 5,14,28,36,42,56,58,64 6 [1] 120 160 [2] ma 3.3v power supply volta ge 18,30,47,54,60 3.0 3.3 3.6 v 3.3v power supply current 18,30,47,54,60 6 [1] 45 50 [2] ma input clock frequency 61 4.000 mhz a mbient operation temperature 0 20 70 [1]conditions: stand - by mode [2]conditions: symbol rate 44.9msps, code rate 7/8, an d ts serial output. 8.2 absolute maximum ratings parameters pins min max units 1.8v power supply voltage 5,14,28,36,42,56,58,64 - 0.3 2.0 v 3.3v power supply voltage 18,30,47,54,60 - 0.3 3.6 v voltage on i/o pins - 0.3 5.5 v storage temperature - 65 150 operating ambient temperature 0 70 junction temperature 0 125 8.3 dc electronic characteristics parameters pins min typ max units 1.8v power supply voltage 5,14,28,36,42,56,58,64 1.62 1.80 1.98 v 1.8v power supply current 5,14,28,36,42,56,58,64 6 [1] 120 160 [2] ma 3.3v power supply voltage 18,30,47,54,60 3.0 3.3 3.6 v 3.3v power supply current 18,30,47,54,60 6 [1] 45 50 [2] ma output high level (voh) 2.4 v output low level (vol) 0.4 v output drive strength 24 ma input high level (vih) 2.0 5.5 v input low level (vil) - 0.3 0.8 v input leakage current 10 ua free datasheet http://www..net/
gx1101 family 39 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com [1]conditions: stand - by mode [2]conditions: symbol rate 44.9msps, code rate 7/8, and ts serial output. 8.4 gx1101p register map 8.4.1 read/write register map name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default stby 01h standby ts_oen 6 b0 r/w 00h pll kn 02h pll_k pll_n pll_m[8] r/w c0h pl l m 03h pll_m[7:0] r/w b2h adc gain 04h 6 b0 adc_gain r/w 01h diseqc mode 10h reserved hv select tx_bytes diseqc_mode r/w 00h diseqc ratio 11h diseqc_ratio r/w 2dh diseqc ins 12h diseqc_ins r/w 00h diseqc ctrl 1bh reserved min_pulse max_ tone min_ ton e r/w 0ch glb ctrl 30h reserved rpt_time_ sel cool_ rst hot_ rst rpter_ en r/w 0ah gpop0 31h reserved 1 b 1 po0/aud_out r/w 16h gpop1 32h reserved 4 b1100 po1 r/w 18h agc ctrl 40h freeze clk speed plr 1 b0 r/w 52h agc std 41h agc_std r/w 1ch freq err 1 l 50h freq_err1 [7:0] r/w 00h freq err1 h 51h freq_err1 [15:8] r/w 00h audio derot 55h audio_on drt_on 6 b101110 r/w 6eh iq swap 58h iq_sp 7 b0110100 r/w 34h crl para 59h crl_para r/w 58h blind sel 60h reserved set to 7 b0 bld mod r/w 00h sym rate l 61h sym_rate [7:0] r/w aeh sym rate h 62h sym_rate [15:8] r/w 11h trl para 69h trl_para r/w 24h scan len 6bh 4 b0110 scan_len r/w 67h vit err mode 80h reserved vit_err_cnt_mod r/w 11h free datasheet http://www..net/
gx1101 family 40 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com vit mode 85h 3 b0 aut_ iq vit_rat aut_ rat r/w 10h rs err mode a0h reserved cnt_knd err_knd r/w 07h ts data ctrl b0h tei_en pkt_ len head 5 b11101 r/w bdh ts fmt ctrl b1h po_en pos_en 4 b1011 rs0 1 b0 r/w ach 8.4.2 read only register map name addr b7 b6 b5 b4 b3 b2 b1 b0 flag default id 00h id [7:0] chip id entification r 01h diseqc int 1ch rx_bytes tx_int silent _int end_ msg_int err_ int par_err _int r 00h diseqc resp 1eh diseqc_resp r 00h state 34h state_indicator r 00h blind state 35h blind_state_indicator r 00h intensity 42h signal_intensity r 00h f req err2 l 52h freq_err2 [7:0] r 00h freq err2 h 53h freq_err2 [15:8] r 00h snr 54h snr [7:0] r 00h vit err cnt l 81h vit_err_cnt [7:0] r 00h vit err cnt m 82h vit_err_cnt [15:8] r 00h vit err cnt h 83h vit_err_cnt [23:16] r 00h vit rat 84h vit_ rat reserved r 00h rs err cnt l a1h rs_ err_cnt [7:0] r 00h rs err cnt h a2h rs_err_cnt [15:8] r 00h free datasheet http://www..net/
gx1101 family 41 addr : 5f east software park innovation building, no.99 huaxin g road, hangzho u p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 8.5 a pplication s chematic 8.5.1 adc external circuit the gx1101p supports both differential and single - ended mode input, and the common mode voltage (vcm) is 0.6*avdd. so, resister dividers between avdd and agnd are necessary for this dc bias, as shown in figure11 and figure12. 100nf 50 51 52 53 54 55 49 vbg vinpq vinnq vinpi vinni agnd avdd vrefn vrefp vcm agnd18 avdd18 agnd avdd 47 46 45 43 44 48 42 gx1101 100nf 100nf 2.2uf 2.2uf 100nf 1.8va 100nf 100nf 2.2uf 3.3va 100nf 3.3va 3.3va 2.2uf 100nf 3k4 2k4 tuner 0.1uf4 q+ i- q- i+ 2.2uf 2.2uf figure 11 differential mode 100nf 50 51 52 53 54 55 49 vbg vinpq vinnq vinpi vinni agnd avdd vrefn vrefp vcm agnd18 avdd18 agnd avdd 47 46 45 43 44 48 42 gx1101 100nf 100nf 2.2uf 2.2uf 100nf 1.8va 100nf 2.2uf 3.3va 3.3va 3.3va 2.2uf 100nf 3k4 2k4 tuner 0.1uf4 q i 2.2uf 100nf 2.2uf figure 12 single - ended mode free datasheet http://www..net/
gx1101 family 42 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 8.5.2 crystal and pll parallel resonant fundamental frequency (typ.) 4mhz tolerance overall 50ppm tolerance over operating temperature range 25ppm equivalent series resistance <50ohm nominal load capacitance 30pf 57 58 59 60 61 62 56 vsspll dvdd33 xout xin gx1101 63 vddpll vsspll vddpll dvss33 33pf 33pf 4mhz 1m 3.3vd 2.2uf 100nf 1.8va 2.2uf 100nf 1.8va 2.2uf 100nf pll c1 c2 r figure 13 crystal and pll note: 1, the crystal frequency is flexible, but users should confirm the system clock frequency is no less than two times of the highest symbol rate, 2, in figure13, c1 and c2 are determined by the crystal s load capacitance. we suggest users to adjust their values slightly to get a precise enough oscillation frequency. 3, gx1101 s clock may be driven by another ic. to do this, please remove the crystal and the two capacitor s, connect another ic s clkout pin to gx1101 s xin pin through a 0.1uf capacitor , and remain the feed - back resister (1mohm). this circuit is shown in figure 14. 61 62 xout xin gx1101 0.1uf 1m c r another ic clkout figure 14 gx1101 s clock driven by another ic 8.5.3 agc circuit free datasheet http://www..net/
gx1101 family 43 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com most of the tuners have maximum (v max ) and minimum (v min ) control voltage limits. if the control voltage (v agc ) is higher than v max , the tuner may be destroyed. on the other hand, if v agc is lower than v min , it is out of agc effective range. users can get v max and v min from tuner s agc curve. to make best use of agc effe ctive range, we provide a general circuit, as shown in figure15. agc gx1101 r o rs r p agc tuner r t vdda agnd r c 40k 4 0 1k 10k 22nf r l figure 15 agc the components can be derived by: (1) r*c=0.2ms (2) vdda*(r l //r t )/((r l //r t )+r+r p )= v max (3) vdda*(r s +r o ) /(r p +r s +r o )= v min (r s , r o , r p << r, r l , r t ) where ro is about 50ohm, vdda is 5v or 3.3v. if v min =0, rs is equal to 0. 8.5.4 lnb c ontroller 7 6 8 gx1101 hvselect diseqc diseqcout diseqcin lm317 in out adj 22nf 22va 3.3va 3 2 1 lnb 150k 2.2k 2.2k 22k 2.2k t1 t3 t2 1.25k 44k 15k 100uh(r <0.5) 0.5uf 15 1000pf 50k 220 22 1000pf 30v 17v/13v figure 16 lnb power suppl y and control the receive part is only necessary for diseqc tm 2.x versions. for diseqc tm 1.x versions, free datasheet http://www..net/
gx1101 family 44 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com pin6 should be connected to the ground. 8.5.5 power sequence in order to avoid latch, please confirm the core powers (1.8v) are built behind the i/o powe rs (3.3v). free datasheet http://www..net/
gx1101 family 45 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 9 block diagram adcs aaf & interpolation & nyquist filter viterbi decoder agc output formatter ram carrier recovery rs decoder descrambler d [ 7 : 0 ] d a t v l d e r r o r s y n c b y t c l k vinpi agc serial 2-wire bus & repeater d e v a d d r s c l s d a s c l t s d a t to internal registers clock generator x i n x o u t dc comp. derotator derotator carrierlock indicator timinglock indicator deinterleaver diseqc contol diseqcin diseqcout vinni vinnq vinpq search mode control free datasheet http://www..net/
gx1101 family 46 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 10 application diagram zif down convertor rf in 950 2150mhz vinpq vinnq lnb power &control rc filter agc agc dual-adc gx1101 diseqcout hvselect diseqcin sclt sdat bus repeater diseqc v2.2 crystal 4mhz mpeg2 ts output d0..d7 error datvld sync bytclk mcu/ mpu sda scl nrst vinpi vinni free datasheet http://www..net/
gx1101 family 47 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 11 pin information 11.1 pin diagram gx1101p (lqfp64/tqfp64) 29 28 27 26 25 24 23 22 21 20 19 18 32 31 30 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 2 3 4 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 17 49 vbg vinpq vinnq vinpi vinni vddpll vsspll dvdd33 vddpll vsspll agnd avdd xin xout dvss33 agc sda scl sclt sdat error datvld dvdd18 dvss18 nrst diseqcout hvselect diseqcin dvdd18 dvss18 dvss18 sync bytclk d7 d6 d5 d4 dvdd33 dvss33 dvdd18 d3 d2 d1 d0 dvdd33 dvss18 dvss33 vrefn vrefp testen biststart biststatus devaddr scanen vcm agnd18 avdd18 agnd avdd gpop0 gpop1 dvss18 dvdd18 dvdd18 free datasheet http://www..net/
gx1101 family 48 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 11.2 pin description pin name dir description 1 sclt od serial clock of the 2 - wire bus for t uner, open - drain output, 5v tolerant. 2 sdat i/od serial data of the 2 - wire bus for tuner, open - drain bi - direction, 5v tolerant. 10 sda i/od serial data of the 2 - wire bus for gx1101p, open - drain bi - direction, 5v tolerant. 11 scl i serial clock of the 2 - wire bus for gx1101p, 5v tolerant. 37 devaddr i address select for 2 - wire bus, 5v tolerant, read address is: 110100a1, write address is: 110100a0. 4 agc od pdm output for agc, open - drain output, 5v tolerant. 6 diseqcin i diseqc input signal, 5v toler ant. 7 diseqcout o diseqc output signal. 8 hvselect o h orizontal or vertical polarization select output for the lnb controller , refer to register 10h. 12 nrst i chip reset, active low, 5v tolerant. to get an effective reset, the low pulse width must be longer than 2us. 15 error o packet error signal of mpeg2 - ts. 16 datvld o data valid signal of mpeg2 - ts. 17 sync o packet s ynchronize signal of mpeg2 - ts. 19 bytclk o byte clock of mpeg2 - ts, it is bit clock in serial output mode. 21 - 26, 31 - 32 d[7:0] o data output of mpeg2 - ts, d[7] is serial data in serial output mode. 33 gpop0 o programmable output, refer to register 31h, 0 default. free datasheet http://www..net/
gx1101 family 49 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 34 gpop1 o programmable output, refer to register 32h, 1 default. 38 scanen i scan test enable of register chain, activ e high, just for manufactory test and connect to 0 in normal operation mode. 39 biststart i built - in self - test (bist) start signal, active high, just for test and connect to 0 in normal operation mode. 40 biststatus o built - in self - test (bist) status ou tput signal, just for test. 41 testen i test enable, active high, just for manufactory test and connect to 0 in normal operation mode. 42 avdd18 pow analog positive power supply for adc (1.8v) 43 agnd18 pow analog negative power supply for adc (gnd). 4 4 vrefn o negative reference voltage output to be decoupled with external capacitors: 100nf between vrefn and agnd, and 2.2uf//100nf between vrefp and vrefn. 45 vrefp o positive reference voltage output to be decoupled with external capacitors: 100nf betw een vrefp and agnd, and 2.2uf//100nf between vrefp and vrefn. 46 vcm o common mode voltage output to be decoupled with external capacitors: 2.2uf//100nf between vcm and agnd. 47,54 avdd pow analog positive power supply for adc (3.3v). 48,55 agnd pow an alog negative power supply for adc (gnd). 49 vbg o band - gap voltage output to be decoupled with external capacitors: 2.2uf//100nf between vbg and agnd. 50 vinpq i voltage input positive of base - band signal q. 51 vinnq i voltage input negative of base - ba nd signal q. 52 vinni i voltage input negative of base - band signal i. 53 vinpi i voltage input positive of base - band signal i. 56,58 vddpll pow analog positive power supply for pll (1.8v). 57,59 vsspll pow analog negative power supply for pll (gnd). free datasheet http://www..net/
gx1101 family 50 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 61 xin i crystal input. 62 xout o crystal output. 5,14,2 8,36,6 4 dvdd18 pow digital positive power supply for core (1.8v). 3,9,13 ,27,35 dvss18 pow digital negative power supply for core(gnd). 18,30 ,60 dvdd33 pow digital positive power supply for i/o(3 .3v). 20,29 ,63 dvss33 pow digital negative power supply for i/o (gnd). free datasheet http://www..net/
gx1101 family 51 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com 12 package information detail of lead end q s r b a c d j h g f m k l p item millimeters inches a 12.00.4 0.4720.016 b 10.00.2 0.3940.008 c 10.00.2 0.3940.008 d 12.00.4 0.4720.016 f 1.250.1 0.0490.004 g 1.250.1 0.0490.004 h 0.20.1 0.0080.004 i 0.13 0.005 j 0.5 (t.p.) 0.020 (t.p.) k 1.00.2 0.0390.008 l 0.50.2 0.0200.008 m +0.10 0.127 - 0.05 +0.004 0.005 - 0.002 n 0.10 0.004 p 1.4 (t.p.) 0.055 (t.p.) free datasheet http://www..net/
gx1101 family 52 addr : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china , 310012 tel : + 86 - 571 - 8 8156088 fax: + 86 - 571 - 88156081 http://www . nationalchip.com history date version note 2004 - 05 1.0 first version. 2004 - 07 1.3 update registers: 59h, 69h, and add a clock drive circuit. 2004 - 08 1.4 update according to nre. 2004 - 12 1.5 update register b1h 2005 - 02 1.6 update pin list, 10uf - >2.2uf addrress : 5f east software park innovation building, no.99 huaxin g road, hangzhou p.r.china, zip code: 310012 tel: + 86 - 571 - 88156080, 88156088 - 858 fax: + 86 - 571 - 88156081, 88156083 e - mail: marketing@ nationalchip.com websit: http://www.nationalchip.com free datasheet http://www..net/

▲Up To Search▲

Price & Availability of QX1101

	To Download QX1101 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .